What's wrong with my VHDL testbench? -

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i've created testbench test adder carry circuit (although doesn't matter circuit doing)

you can see below i'm getting 'error' failures spit out testbench.at 261901ps, show values here in isim debugger.. test_s(8) , (0) both '1' , cout '1'.

enter image description here

now, testbench looks this:

assert (test_s(8) = cout)     report "carry out failed cin = 1!";

so what's wrong? tried /= cout in case.. , seem same thing. want say, if test_s msb (8) different cout, issue error because that's broken behavior

cout std_logic; test_s std_logic_vector(8 downto 0);

your vhdl correct. asserting test_s(8) should equal cout , report when not.

at cursor on waveform, test_s(8) 0 , cout 1. assert detecting , reporting it.


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