makefile - Define compilation variables based on target for -

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my c++ source file specific variable passed makefile. when making different target, variable definition different.

how can define variable in makefile based on target.

thanks

you can use target-specific variable values, propagate target's prerequisites: 

all : foo bar foo : cxxflags += -dfoo bar : cxxflags += -dbar  foo bar :     @echo target=$@ cxxflags=${cxxflags}  .phony :

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