c - Cortex: NVIC, please demostrate how to make it level or edge detects by software -

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i have read arm document cortex-m3 (or m0) , can used level sensetive or pulse (edge) interrupt within nvic controller. problem rather vague on how this, if done software.

i fails see kind of register within nvic or such control type of interrupt (to select edge or level adjusting register bits). must done software within handler again vague in field.

i hear having way make edge or level trigger interrupt software.

please demonstrate within handler code (if control it) make detect level or pulse.

if level detect, can hold interrupt active , disable handler, until restore external code re-excute interrupt. i'm trying do, not work if pulse detect type.

thx

a document describes how cortex-m3 nivc handles level or edge (pulse) triggered interrupts can found here:

this may document refer in question. joseph yiu's book, "the definitive guide arm cortex-m3" has pretty description.

there no particular configuration of nvic these 2 interrupt signal types - handles either kind. essentially, when interrupt asserted (whterh level-based or edge triggered) nvic latches status in setpendx register. when isr interrupt vectored to, corresponding bit in activex register set , bit in setpendx register cleared.

while interrupt active, if interrupt line transitions inactive active, pending bit turned on again, , upon return current active isr instance, interrupt handled again. handles edge triggered interrupt case.

also, when isr returns (and nvic clears 'active' bit), nivc reexamine state of interrupt line - if it's still asserted set pending bit again (even if there hasn't been a transition inactive active). handles case interrupt level triggered, , isr didn't manage cause interrupt de-asserted (maybe second device on shared irq line asserted interrupt @ critical moment there no time when interrupt line inactive).

if level detect, can hold interrupt active , disable handler, until restore external code re-execute interrupt.

i'm not sure understand you're after here, think might able want using nvic's setenax , clrenax registers enable/disable interrupt. these work independently of pending bits, interrupt can pending (or become pending) if interrupt disabled. can hold off handling interrupt long want.

if that's not quite enough, note can cause interrupt pend via software setting pending bit in corresponding setpendx register - cpu vector isr if hardware interrupt asserted (assuming interrupt enabled in setenax register). can use "software trigger interrupt register" (stir) trigger interrupt software.


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